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ADP1043A
Table 124. Register 0x4F—OUTD Fallin g Edge Dead Time in Resonant Mode
Bits
[7:0]
Name
Δt 8 (falling edge dead
time of OUTD)
R/W
R/W
Description
This register sets Δt 8 , which is the leading time of the falling edge of OUTD from the end of the
switching cycle, t C . Each LSB corresponds to 5 ns of resolution.
Bit 7
0
0
…
1
Bit 6
0
0
…
1
Bit 5
0
0
…
1
Bit 4
0
0
…
1
Bit 3
0
0
…
1
Bit 2
0
0
…
1
Bit 1
0
0
…
1
Bit 0
0
1
…
1
Δt 8 (ns)
0
5
…
1275
Table 125. Register 0x51—SR1 Rising Edge Dead Time in Resonant Mode
Bits
[7:0]
Name
Δt 9 (rising edge dead
time of SR1)
R/W
R/W
Description
This register sets Δt 9 , which is the delay time of the rising edge of SR1 from the ACSNS rising
edge, t D . Each LSB corresponds to 5 ns of resolution.
Bit 7
0
0
…
1
Bit 6
0
0
…
1
Bit 5
0
0
…
1
Bit 4
0
0
…
1
Bit 3
0
0
…
1
Bit 2
0
0
…
1
Bit 1
0
0
…
1
Bit 0
0
1
…
1
Δt 9 (ns)
0
5
…
1275
Table 126. Register 0x53—SR1 Falling Edge Dead Time in Resonant Mode
Bits
[7:0]
Name
Δt 10 (falling edge
dead time of SR1)
R/W
R/W
Description
This register sets Δt 10 , which is the leading time of the falling edge of SR1 from the ACSNS
falling edge, t E . Each LSB corresponds to 5 ns of resolution.
Bit 7
0
0
…
1
Bit 6
0
0
…
1
Bit 5
0
0
…
1
Bit 4
0
0
…
1
Bit 3
0
0
…
1
Bit 2
0
0
…
1
Bit 1
0
0
…
1
Bit 0
0
1
…
1
Δt 10 (ns)
0
5
…
1275
Table 127. Register 0x55—SR2 Rising Edge Dead Time in Resonant Mode
Bits
[7:0]
Name
Δt 11 (rising edge dead
time of SR2)
R/W
R/W
Description
This register sets Δt 11 , which is the delay time of the rising edge of SR2 from the ACSNS falling
edge, t E . Each LSB corresponds to 5 ns of resolution.
Bit 7
0
0
…
1
Bit 6
0
0
…
1
Bit 5
0
0
…
1
Bit 4
0
0
…
1
Bit 3
0
0
…
1
Bit 2
0
0
…
1
Bit 1
0
0
…
1
Bit 0
0
1
…
1
Δt 11 (ns)
0
5
…
1275
Table 128. Register 0x57—SR2 Falling Edge Dead Time in Resonant Mode
Bits
[7:0]
Name
Δt 12 (falling edge
dead time of SR2)
R/W
R/W
Description
This register sets Δt 12 , which is the leading time of the falling edge of SR2 from the ACSNS rising
edge, t F . Each LSB corresponds to 5 ns of resolution.
Bit 7
0
0
…
1
Bit 6
0
0
…
1
Bit 5
0
0
…
1
Bit 4
0
0
…
1
Bit 3
0
0
…
1
Bit 2
0
0
…
1
Bit 1
0
0
…
1
Bit 0
0
1
…
1
Δt 12 (ns)
0
5
…
1275
Rev. 0 | Page 70 of 72
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